1. Field of the Invention
The present invention relates to the field of defect monitoring; more specifically, it relates to a method of inserting a test circuit and corresponding shorts/opens defect monitoring structures into an integrated circuit design.
2. Background of the Invention
Yield management in integrated circuit manufacturing is an ongoing concern and is especially important as new technologies, tools and processes are developed and introduced into manufacturing. As integrated circuits have become more complex, yield learning has become more difficult and defect monitor circuits and structures have become increasing more difficult to insert into integrated circuit chips, especially application specific integrated circuit (ASIC) chips where chip area available for defect monitoring may be at a premium and the functional design may be generated separately from defect monitor circuits and structures. Further, traditional placement sites, such as kerfs, often require too much area (and are thus expensive) for sufficiently large monitor structures. Therefore, there is a need for a method to insert defect monitoring circuits, and defect monitoring structures into integrated circuit designs.